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ISL5961
Data Sheet September 2001 FN6007.2
14-Bit, +3.3V, 130/210+MSPS, High Speed D/A Converter
The ISL5961 is a 14-bit, 130/210+MSPS (Mega Samples Per Second), CMOS, high speed, low power, D/A (digital to analog) converter, designed specifically for use in high performance communication systems such as base transceiver stations utilizing 2.5G or 3G cellular protocols. This device complements the ISL5x61 family of high speed converters, which include 10, 12, and 14-bit devices.
Features
* Speed Grades . . . . . . . . . . . . . . . . 130M and 210+MSPS * Low Power . . . . . 103mW with 20mA Output at 130MSPS * Adjustable Full Scale Output Current . . . . . 2mA to 20mA * +3.3V Power Supply * 3V LVCMOS Compatible Inputs * Excellent Spurious Free Dynamic Range (75dBc to Nyquist, f S = 130MSPS, fOUT = 10MHz) * UMTS Adjacent Channel Power =71dB at 19.2MHz * EDGE/GSM SFDR = 94dBc at 11MHz in 20MHz Window
Ordering Information
PART NUMBER ISL5961IB ISL5961IA ISL5961/2IB ISL5961/2IA ISL5961EVAL1 TEMP. RANGE (C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 25 PACKAGE 28 Ld SOIC PKG. DWG. # M28.3 CLOCK SPEED 130MHz
* Pin compatible, 3.3V, Lower Power Replacement For The AD9754 and HI5960
28 Ld TSSOP M28.173 130MHz 28 Ld SOIC M28.3 210MHz
Applications
* Cellular Infrastructure - Single or Multi-Carrier: IS-136, IS95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA * BWA Infrastructure * Medical/Test Instrumentation
28 Ld TSSOP M28.173 210MHz SOIC Evaluation Platform 210MHz
Pinout
ISL5961 TOP VIEW
D13 (MSB) 1 D12 2 D11 3 D10 4 D9 5 D8 6 D7 7 D6 8 D5 9 D4 10 D3 11 D2 12 D1 13 D0 (LSB) 14 28 CLK 27 DVDD 26 DCOM 25 NC 24 AVDD 23 COMP 22 IOUTA 21 IOUTB 20 ACOM 19 NC 18 FSADJ 17 REFIO 16 REFLO 15 SLEEP
* Wireless Communication Systems * High Resolution Imaging Systems * Arbitrary Waveform Generators
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001, All Rights Reserved
ISL5961 Typical Applications Circuit
ISL5961 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 (1) D12 (2) D11 (3) D10 (4) D9 (5) D8 (6) D7 (7) D6 (8) D5 (9) D4 (10) D3 (11) D2 (12) D1 (13) D0 (LSB) (14) CLK (28) 50 BEAD + 10F 10H 0.1F DVDD (27) DCOM (26) (20) ACOM (24) AVDD (23) COMP 0.1F FERRITE BEAD 10H 0.1F 10F + +3.3V (VDD) (21) IOUTB 1:1, Z1:Z2 (22) IOUTA 50 (50) REPRESENTS ANY 50 LOAD (18) FSADJ RSET 1.91k (25, 19) NC (15) SLEEP (16) REFLO (17) REFIO 0.1F ONE CONNECTION DCOM ACOM
Functional Block Diagram
IOUTA IOUTB
(LSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 40 INPUT LATCH CASCODE CURRENT SOURCE
SWITCH MATRIX
40
9 LSBs + 31 MSB SEGMENTS
D10
D11 D12 (MSB) D13 COMP CLK INT/EXT VOLTAGE REFERENCE BIAS GENERATION UPPER 5-BIT DECODER
REFLO REFIO
FSADJ
SLEEP
2
ISL5961 Pin Descriptions
PIN NO. 1-14 PIN NAME D13 (MSB) Through D0 (LSB) SLEEP DESCRIPTION Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
15
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20A active pulldown current. Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0.1F cap to ground when internal reference is enabled. Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET. No Connect. These should be grounded, but can be left disconnected. The complementary current output of the device. Full scale output current is achieved when all input bits are set to binary 0. Current output of the device. Full scale output current is achieved when all input bits are set to binary 1. Connect 0.1F capacitor to ACOM. Analog Supply (+2.7V to +3.6V). Connect to Analog Ground. Connect to Digital Ground. Digital Supply (+2.7V to +3.6V). Clock Input.
16 17
REFLO REFIO
18
FSADJ
19, 25 21
NC IOUTB
22 23 24 20 26 27 28
IOUTA COMP AVDD ACOM DCOM DVDD CLK
3
ISL5961
Absolute Maximum Ratings
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . . +3.6V Analog Supply Voltage AVDD to ACOM . . . . . . . . . . . . . . . . . . +3.6V Grounds, ACOM TO DCOM. . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DVDD + 0.3V Reference Input Voltage Range . . . . . . . . . . . . . . . . . . AVDD + 0.3V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA(oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL Offset Error, IOS Offset Drift Coefficient Full Scale Gain Error, FSE
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values TA = -40oC TO 85oC TEST CONDITIONS MIN TYP MAX UNITS
14 "Best Fit" Straight Line (Note 7) (Note 7) IOUTA (Note 7) (Note 7) With External Reference (Notes 2, 7) With Internal Reference (Notes 2, 7) -5 -3 -0.006 -3 -3 2 (Note 3) -1.0
2.5 1.5
+5 +3 +0.006
Bits LSB LSB % FSR ppm FSR/oC % FSR % FSR ppm FSR/oC ppm FSR/oC mA V
0.1 0.5 0.5 50 100 -
+3 +3 20 1.25
Full Scale Gain Drift
With External Reference (Note 7) With Internal Reference (Note 7)
Full Scale Output Current, IFS Output Voltage Compliance Range DYNAMIC CHARACTERISTICS Maximum Clock Rate, fCLK Maximum Clock Rate, fCLK Output Rise Time Output Fall Time Output Capacitance Output Noise IOUTFS = 20mA IOUTFS = 2mA AC CHARACTERISTICS (Using Figure 13 with RDIFF = 50 and RLOAD= 50, Full Scale Output = -2.5dBm) Spurious Free Dynamic Range, SFDR Within a Window fCLK = 210MSPS, fOUT = 80.8MHz, 30MHz Span (Notes 4, 7) fCLK = 210MSPS, fOUT = 40.4MHz, 30MHz Span (Notes 4, 7) fCLK = 130MSPS, fOUT = 20.2MHz, 20MHz Span (Notes 4, 7) ISL5961/2IA, ISL5961/2IB ISL5961IA, ISL5961IB Full Scale Step Full Scale Step
210 130 -
250 150 1.5 1.5 10 50 30
-
MHz MHz ns ns pF pA/Hz pA/Hz
-
73 82 86
-
dBc dBc dBc
4
ISL5961
Electrical Specifications
PARAMETER Spurious Free Dynamic Range, SFDR to Nyquist (fCLK/2) AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) TA = -40oC TO 85oC TEST CONDITIONS fCLK = 210MSPS, fOUT = 80.8MHz (Notes 4, 7) fCLK = 210MSPS, fOUT = 40.4MHz (Notes 4, 7, 9) fCLK = 200MSPS, fOUT fCLK = 200MSPS, fOUT = 20.2MHz, T = 25oC (Notes 4, 7) = 20.2MHz, T = -40oC to 85oC (Notes 4, 7) MIN 62 60 72 70 TYP 52 61 64 59 63 70 75 79 61 65 71 71 78 70 75 79 67 70 77 78 94 71 MAX UNITS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB
fCLK = 130MSPS, fOUT = 50.5MHz (Notes 4, 7) fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 7) fCLK = 130MSPS, fOUT = 20.2MHz (Notes 4, 7) fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 7) fCLK = 130MSPS, fOUT fCLK = 130MSPS, fOUT = 5.05MHz, T = 25oC (Notes 4, 7) = 5.05MHz, T = -40oC to 85oC (Notes 4, 7)
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 7) fCLK = 80MSPS, fOUT = 30.3MHz (Notes 4, 7) fCLK = 80MSPS, fOUT = 20.2MHz (Notes 4, 7) fCLK = 80MSPS, fOUT = 10.1MHz (Notes 4, 7, 9) fCLK = 80MSPS, fOUT = 5.05MHz (Notes 4, 7) fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 7) fCLK = 50MSPS, fOUT = 10.1MHz (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.05MHz (Notes 4, 7) Spurious Free Dynamic Range, SFDR in a Window with Eight Tones fCLK = 210MSPS, fOUT = 28.3MHz to 45.2MHz, 2.1MHz Spacing, 50MHz Span (Notes 4, 7, 9) fCLK = 130MSPS, fOUT =17.5MHz to 27.9MHz, 1.3MHz Spacing, 35MHz Span (Notes 4, 7) fCLK = 80MSPS, fOUT = 10.8MHz to 17.2MHz, 811kHz Spacing, 15MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 6.7MHz to 10.8MHz, 490kHz Spacing, 10MHz Span (Notes 4, 7) Spurious Free Dynamic Range, fCLK = 78MSPS, fOUT = 11MHz, in a 20MHz Window, RBW=30kHz SFDR in a Window with EDGE or GSM (Notes 4, 7, 9) Adjacent Channel Power Ratio, ACPR with UMTS VOLTAGE REFERENCE Internal Reference Voltage, VFSADJ Internal Reference Voltage Drift Internal Reference Output Current Sink/Source Capability Reference Input Impedance Reference Input Multiplying Bandwidth (Note 7) DIGITAL INPUTS D13-D0, CLK (Note 3) (Note 3) Reference is not intended to be externally loaded Pin 18 Voltage with Internal Reference fCLK = 76.8MSPS, fOUT = 19.2MHz, RBW=30kHz (Notes 4, 7, 9)
1.2 -
1.23 40 0 1 1.0
1.3 -
V ppm/oC A M MHz
Input Logic High Voltage with 3.3V Supply, VIH Input Logic Low Voltage with 3.3V Supply, VIL Sleep Input Current, IIH
2.3 -25
3.3 0 -
1.0 +25
V V A
5
ISL5961
Electrical Specifications
PARAMETER Input Logic Current, IIH, IL Clock Input Current, IIH, IL Digital Input Capacitance, CIN TIMING CHARACTERISTICS Data Setup Time, tSU Data Hold Time, tHLD Propagation Delay Time, tPD CLK Pulse Width, tPW1 , tPW2 See Figure 15 See Figure 15 See Figure 15 See Figure 15 (Note 3) 2 1.5 1.5 1 ns ns Clock Period ns AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) TA = -40oC TO 85oC TEST CONDITIONS MIN -20 -10 TYP 5 MAX +20 +10 UNITS A A pF
POWER SUPPLY CHARACTERISTICS AVDD Power Supply DVDD Power Supply Analog Supply Current (IAVDD) (Note 8) (Note 8) 3.3V, IOUTFS = 20mA 3.3V, IOUTFS = 2mA Digital Supply Current (IDVDD) 3.3V (Note 5) 3.3V (Note 6) Supply Current (IAVDD) Sleep Mode Power Dissipation 3.3V, IOUTFS = Don't Care 3.3V, IOUTFS = 20mA (Note 5) 3.3V, IOUTFS = 20mA (Note 6) 3.3V, IOUTFS = 2mA (Note 5) Power Supply Rejection NOTES: 2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625A). Ideally the ratio should be 32. 3. Parameter guaranteed by design or characterization and not production tested. 4. Spectral measurements made with differential transformer coupled output and no external filtering. For multitone testing, the same pattern was used at different clock rates, producing different output frequencies but at the same ratio to the clock rate. 5. Measured with the clock at 130MSPS and the output frequency at 5MHz. 6. Measured with the clock at 200MSPS and the output frequency at 20MHz. 7. See "Definition of Specifications." 8. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in analog output current may be necessary to maintain spectral performance. 9. See Typical Performance Plots. Single Supply (Note 7) 2.7 2.7 -0.125 3.3 3.3 27.5 10 3.7 6.5 1.5 103 110 45 3.6 3.6 28.5 5 8 111 120 +0.125 V V mA mA mA mA mA mW mW mW %FSR/V
6
ISL5961 Typical Performance (+3.3V Supply, Using Figure 13 with RDIFF = 100 and RLOAD= 50)
SPECTRAL MASK FOR GSM900/DCS1800/PCS1900 P>43dBm NORMAL BTS WITH 30kHz RBW
FIGURE 1. EDGE AT 11MHz, 78MSPS CLOCK (94+dBc @ f = +6MHz)
FIGURE 2. EDGE AT 11MHz, 78MSPS CLOCK (77dBc -NYQUIST, 6dB PAD)
SPECTRAL MASK FOR GSM900/DCS1800/PCS1900 P>43dBm NORMAL BTS WITH 30kHz RBW
FIGURE 3. GSM AT 11MHz, 78MSPS CLOCK (94+dBc @ f = +6MHz, 3dB PAD)
FIGURE 4. GSM AT 11MHz, 78MSPS CLOCK (79dBc - NYQUIST, 9dB PAD)
FIGURE 5. FOUR EDGE CARRIERS AT 12.4-15.6MHz, 800kHz SPACING, 78MSPS (75+dBc - 20MHz WINDOW)
FIGURE 6. FOUR GSM CARRIERS AT 12.4-15.6MHz, 78MSPS (75+dBc - 20MHz WINDOW, 6dB PAD)
7
ISL5961 Typical Performance (+3.3V Supply, Using Figure 13 with RDIFF = 100 and RLOAD= 50)
(Continued)
SPECTRAL MASK UMTS TDD P>43dBm BTS
FIGURE 7. UMTS AT 19.2MHz, 76.8MSPS (71dB 1stACPR, 75dB 2ndACPR)
FIGURE 8. ONE TONE AT 10.1MHz, 80MSPS CLOCK (71dBc NYQUIST, 6dB PAD)
FIGURE 9. ONE TONE AT 40.4MHz, 210MSPS CLOCK (61dBc - NYQUIST, 6dB PAD)
FIGURE 10. EIGHT TONES (CREST FACTOR=8.9) AT 37MHz, 210MSPS CLOCK, 2.1MHz SPACING (65dBc - NYQUIST)
FIGURE 11. TWO TONES (CF=6) AT 8.5MHz, 50MSPS CLOCK, 500kHz SPACING (83dBc - 10MHz WINDOW, 6dB PAD)
FIGURE 12. FOUR TONES (CF=8.1) AT 14MHz, 80MSPS CLOCK, 800kHz SPACING (70dBc - NYQUIST, 6dB PAD)
8
ISL5961 Definition of Specifications
Adjacent Channel Power Ratio, ACPR, is the ratio of the average power in the adjacent frequency channel (or offset) to the average power in the transmitted frequency channel. Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. EDGE, Enhanced Data for Global Evolution, a TDMA standard for cellular applications which uses 200kHz BW, 8PSK modulated carriers. Full Scale Gain Drift, is measured by setting the data inputs to be all logic high (all 1s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per oC. Full Scale Gain Error, is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through RSET). GSM, Global System for Mobile Communication, a TDMA standard for cellular applications which uses 200kHz BW, GMSK modulated carriers. Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm per oC. Offset Drift, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage at IOUTA through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per degree oC. Offset Error, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage of IOUTA through a known resistance. Offset error is defined as the maximum deviation of the IOUTA output current from a value of 0mA. Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance should be chosen such that the voltage developed does not violate the compliance range. Power Supply Rejection, is measured using a single power supply. The nominal supply voltage is varied 10% and the change in the DAC full scale output is noted. 9 Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 (-3dB) of its original value. Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental signal to the largest harmonically or non-harmonically related spur within the specified frequency window. Total Harmonic Distortion, THD, is the ratio of the RMS value of the fundamental output signal to the RMS sum of the first five harmonic components. UMTS, Universal Mobile Telecommunications System, a W-CDMA standard for cellular applications which uses 3.84MHz modulated carriers.
Detailed Description
The ISL5961 is a 14-bit, current out, CMOS, digital to analog converter. The maximum update rate is at least 210+MSPS and can be powered by a single power supply in the recommended range of +3.0V to +3.6V. Operation with clock rates higher than 210MSPS is possible; please contact the factory for more information. It consumes less than 120mW of power when using a +3.3V supply, the maximum 20mA of output current, and the data switching at 210MSPS. The architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst-case transition points such as midscale and quarter scale transitions. By greatly reducing the amount of current switching at these major transitions, the overall glitch of the converter is dramatically reduced, improving settling time, transient problems, and accuracy.
Digital Inputs and Termination
The ISL5961 digital inputs are guaranteed to 3V LVCMOS levels. The internal register is updated on the rising edge of the clock. To minimize reflections, proper termination should be implemented. If the lines driving the clock and the digital inputs are long 50 lines, then 50 termination resistors should be placed as close to the converter inputs as possible connected to the digital ground plane (if separate grounds are used). These termination resistors are not likely needed as long as the digital waveform source is within a few inches of the DAC. For pattern drivers with very high speed edge rates, it is recommended that the user consider series termination (50-200) prior to the DAC's inputs in order to reduce the amount of noise.
ISL5961
Power Supply
Separate digital and analog power supplies are recommended. The allowable supply range is +2.7V to +3.6V. The recommended supply range is +3.0 to 3.6V (nominally +3.3V) to maintain optimum SFDR. However, operation down to +2.7V is possible with some degradation in SFDR. Reducing the analog output current can help the SFDR at +2.7V. The SFDR values stated in the table of specifications were obtained with a +3.3V supply.
TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH INTERNAL REFERENCE AND RSET=1.91K INPUT CODE (D13-D0) 1111 11111 11111 1000 00000 00000 0000 00000 00000 IOUTA (mA) 20 10 0 IOUTB (mA) 0 10 20
Analog Output
IOUTA and IOUTB are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -1.0V to 1.25V. ROUT (the impedance loading each current output) should be chosen so that the desired output voltage is produced in conjunction with the output full scale current. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X ROUT. The most effective method for reducing the power consumption is to reduce the analog output current, which dominates the supply current. The maximum recommended output current is 20mA.
Ground Planes
Separate digital and analog ground planes should be used. All of the digital functions of the device and their corresponding components should be located over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane.
Noise Reduction
To minimize power supply noise, 0.1F capacitors should be placed as close as possible to the converter's power supply pins, AVDD and DVDD. Also, the layout should be designed using separate digital and analog ground planes and these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD. Additional filtering of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal value of +1.23V with a 40ppm/ oC drift coefficient over the full temperature range of the converter. It is recommended that a 0.1F capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (16) selects the reference. The internal reference can be selected if pin 16 is tied low (ground). If an external reference is desired, then pin 16 should be tied high (the analog supply voltage) and the external reference driven into REFIO, pin 17. The full scale output current of the converter is a function of the voltage reference used and the value of RSET. IOUT should be within the 2mA to 20mA range, though operation below 2mA is possible, with performance degradation. If the internal reference is used, VFSADJ will equal approximately 1.2V (pin 18). If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT (Full Scale) is: IOUT(Full Scale) = (VFSADJ/RSET) X 32. If the full scale output current is set to 20mA by using the internal voltage reference (1.2V) and a 1.91k RSET resistor, then the input coding to output current will resemble the following:
Differential Output
IOUTA and IOUTB can be used in a differential-to-singleended arrangement to achieve better harmonic rejection. With RDIFF= 50 and RLOAD=50, the circuit in Figure 13 will provide a 500mV (-2.5dBm) signal at the output of the transformer if the full scale output current of the DAC is set to 20mA (used for the electrical specifications table). Values of RDIFF= 100 and RLOAD=50 were used for the typical performance curves to increase the output power and the dynamic range. The center tap in Figure 13 must be grounded. In the circuit in Figure 14, the user is left with the option to ground or float the center tap. The DC voltage that will exist at either IOUTA or IOUTB if the center tap is floating is IOUTDC x (RA//RB) V because RDIFF is DC shorted by the transformer. If the center tap is grounded, the DC voltage is 0V. Recommended values for the circuit in Figure 14 are RA=RB=50, RDIFF=100, assuming RLOAD=50. The performance of Figure 13 and Figure 14 is basically the same, however leaving the center tap of Figure 14 floating allows the circuit to find a more balanced virtual ground, theoretically improving the even order harmonic rejection, but likely reducing the signal swing available due to the output voltage compliance range limitations.
10
ISL5961
Propagation Delay
REQ = 0.5 x (RLOAD // RDIFF) AT EACH OUTPUT VOUT = (2 x IOUTA x REQ)V 1:1 RDIFF IOUTA RLOAD
IOUTB PIN 21 PIN 22 ISL5961
The converter requires two clock rising edges for data to be represented at the output. Each rising edge of the clock captures the present data word and outputs the previous data. The propagation delay is therefore 1/CLK, plus <2ns of processing. See Figure 15.
Test Service
Intersil offers customer-specific testing of converters with a service called Testdrive. To submit a request, fill out the Testdrive form. The form can be found by doing an `entire site search' at www.intersil.com on the words `DAC Testdrive'. Or, send a request to the technical support center.
RLOAD REPRESENTS THE LOAD SEEN BY THE TRANSFORMER
FIGURE 13. OUTPUT LOADING FOR DATASHEET MEASUREMENTS
REQ = 0.5 x (RLOAD // RDIFF// RA), WHERE RA=RB AT EACH OUTPUT RA IOUTB PIN 21 RDIFF PIN 22 ISL5961 IOUTA RB RLOAD VOUT = (2 x IOUTA x REQ)V
RLOAD REPRESENTS THE LOAD SEEN BY THE TRANSFORMER
FIGURE 14. ALTERNATIVE OUTPUT LOADING
Timing Diagram
tPW1
tPW2
CLK
50%
tSU tHLD D13-D0 W0
tSU tHLD W1
tSU tHLD W2 W3
tPD
tPD OUTPUT=W0
IOUT
OUTPUT=W-1
OUTPUT=W1
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
11
ISL5961 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 10.00 0.25 0.40 28 0o MAX 2.65 0.30 0.51 0.32 18.10 7.60 10.65 0.75 1.27 8o NOTES 9 3 4 5 6 7 Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 0.394 0.01 0.016 28 0o
MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 0.419 0.029 0.050 8o
B C D E e H
C

A1 0.10(0.004)
0.05 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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ISL5961 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.378 0.169 0.246 0.0177 28 0o 8o 0o MAX 0.047 0.006 0.051 0.0118 0.0079 0.386 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 9.60 4.30 6.25 0.45 28 8o MAX 1.20 0.15 1.05 0.30 0.20 9.80 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 0 6/98
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
E1
A2 c
e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AE, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 3-13

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